Embodiments of the present invention relate to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor device using negative spacer patterning.
Today, most electronic appliances include a semiconductor device. The semiconductor device comprises electronic elements such as a transistor, a resistor and a capacitor. These electronic elements are designed to perform a partial function of the electronic device, and integrated on a semiconductor substrate. For example, electronic devices such as a computer and a digital camera include a memory chip for storing information and a processing chip for controlling information. The memory chip and the processing chip include electronic elements integrated on a semiconductor substrate.
There is a need to increase the integration degree of the semiconductor devices in order to satisfy consumer demands for superior performances and low prices. Such an increase in the integration degree entails a reduction in a design rule, causing patterns of a semiconductor device to be increasingly reduced. Although an entire chip area is increased in proportion to an increase in memory capacity, as a semiconductor device becomes super miniaturized and highly integrated, a unit cell area where patterns of a semiconductor device are actually formed is decreased. Accordingly, since a greater number of patterns need to be formed in a limited unit cell area in order to achieve a desired memory capacity, there is a need for formation of microscopic (fine) patterns having a reduced critical dimension scale.
However, an exposure device for implementing a fine pattern required for the increasing integration degree of a semiconductor device does not satisfy rapid development of associated technology. Specifically, a conventional exposure device for an exposure and development process onto a photo resist film has a limitation in resolution capability of the exposure device.
A representative method for forming such a fine pattern is a Double Patterning Technology (DPT). The DPT may be classified into a Double Expose Etch Technology (DE2T) and a Spacer Patterning Technology (SPT) that uses a spacer. The DE2T forms first patterns spaced by a first distance corresponding to a given critical dimension, and exposes a second pattern between the first patterns so that the first and the second patterns are spaced apart by half the given critical dimension.
The spacer pattering technology (SPT) may be classified into a positive spacer patterning technology and a negative patterning technology. 30 nm-level semiconductor devices have been generally patterned using the positive spacer patterning technology.
For example, a 40 nm-level device isolation film has been formed using a conventional single patterning method, and a 30 nm-class 6F2 device isolation film has been formed using the spacer patterning technology. However, when conventional positive spacer patterning is applied for a 20 nm-level 6F2 device isolation film to form an active region, a variety of problems are entailed, for example, collapse of a device isolation film, an insufficient active region, and a reduced patterning margin.
Therefore, the 20 nm-level 6F2 device isolation film must be formed in a line type instead of an island type, and cell isolation is made using a buried gate. In more detail, in addition to two buried gates serving as an active cell gate, two more buried gates are necessary for cell isolation.
When a line-type device isolation film is formed, the isolation buried gates need to be interconnected with each other, and a pad part connected needs to be formed at an end of a gate line used for operation. However, it is difficult for the above-mentioned requirements to be implemented in the conventional positive spacer patterning.